1. Field of the Invention
This invention relates generally to the design of electronic circuits and more particularly to authentication of data files used in simulation and verification of testing procedures.
2. Description of the Related Art
The automated process of designing integrated circuits comprises establishing a netlist and subsequently preparing a layout of the design using layout tools. Once the layout is complete, the layout is simulated and tested to verify the overall performance of the system.
The netlist along with other data, such as testbench and SDF (standard delay format) data, are provided to a simulator, such as a Verilog-XL simulator, for test condition simulation. A worst case commercial condition may also be simulated, i.e. the system may be simulated to have worst case delays or other errors in the system. The results of both simulations compared for mismatches or irregularities. After comparison, the simulation output results from both test condition simulation and worst case commercial condition simulation are submitted to testing, which occurs on a designed chip. Testing includes vector rule checking, WGL file generation, buffer and pin information, and other common procedures.
To assist in performing this physical chip testing procedure, the system uses an Automatic Test Pattern Generation (ATPG) tool. The ATPG tool generates test patterns which permit testing of digital circuitry by toggling all the nodes of the proposed circuit to trace "stuck at" faults, thereby verifying the performance of individual gates. "Stuck at" faults are a result of wires carrying a single signal, either 1 or 0 irrespective of the desired signal due to a short in the system. The ATPG tool can write normal Verilog or VHDL testbench which can simulate the device with a generated pattern and verify that all requirements have been met.
An ATPG tool may generate several types of intermediate files for use during testing. For example, the ATPG tool may generate what are commonly known as .wgl files, .v files, .vhd files, .scl files, or .scf files. A .wgl file includes stimulation data and expected result data, as well as timing information, clock period, and other data for every pin on the device. The .wgl file is an intermediate format, industry standard format which contains intermediate test data. A .v file is a testbench file which has simulation data and expected result data, clock timing data, etc., but is simulatable, and may be used on particular testing tools, such as a Synopsis VSS tool or a Verilog XL or similar simulation tool to verify performance of the system, which cannot be accomplished on an ATPG tool. A .vhd file is a VHDL file format containing test data, an .scl file is a simulation control language file, and a .saf file is a safe file format, which are other intermediate file formats used for specific types of simulators. .saf and .scl files are used for CMDE (Concurrent Modular Design Environment) simulation, and .v and .vhd files are used for VHDL simulation. All these intermediate files contain test data for simulating the circuit. The .v, .vhd, .scl, and .saf files are simulatable, whereas the .wgl file data is not simulatable.
After creating the .wgl file, the specific data from the .wgl file is modified using an additional test program specific test generator, which generates tester specific test program, which is downloaded to the tester, and the tester understands the language and performs the test on the physical silicon device.
The problem associated with these intermediate files is that different tools used by different manufacturers may produce different stimuli data results, or may write out wrong or inconsistent expected results in .wgl or .v files. It is critical that the intermediate files have the same results, so that test and simulation results match identically to give the tester the ability to perform accurate test procedures. Under particular conditions, the ATPG tool may write our different vectors or timing to the v file and the .wgl file.
The problem is that during the test phase a mismatch may be realized by either software or by human visual evaluation, such as by failures of chip performance traced back to improper test results. The difficulty is that the error or mismatch between test and simulation data cannot be easily traced to particular origins; the most that can be said of a mismatch is that a discrepancy between data in intermediate test files has occurred, but the cause of the mismatch cannot readily be pinpointed. The true cause of the test pattern simulation problem cannot be identified.
Currently, the only way for locating the problem associated with an intermediate file mismatch is to create the two intermediate files, pass the intermediate files to the appropriate testing devices, perform the required tests on actual physical silicon, and once a mismatch is detected to report the mismatch or improper test results back to the party or entity who created the tools, such as the ATPG tool, which generate intermediate files with instructions to repair the problem. This method requires testing on actual silicon, and may not be detected for several testing runs, thereby losing time associated with runs occurring before detecting the mismatch and requiring such test runs to be performed more than once. This after-the-fact correction procedure may waste several days or even weeks, and such a holdup during physical testing can be costly and time consuming. In extreme cases, prototypes may have to be put on hold for extended periods of time due to faulty test results.
It is therefore an object of the current invention to provide a system or method for evaluating and improving the quality of intermediate files generated by test pattern generation tools and/or simulations by minimizing the risk of a mismatch between such intermediate files.
It is another object of the current invention to provide a system or method for minimizing disruptions during testing of fully designed and integrated silicon.
It is yet another object of the current invention to provide a system or method of testing physical silicon integrated circuitry using existing file formats, file generation tools, and simulators while at the same time decreasing the chances of encountering improper test results due to multiple file formats.